__ Characteristics in 3D__ Last
updated on

3 dimensional information flows ...; Approx. 12 characteristics are available to read; Also see: IC logical functions; Materials AND circuits; Transistor;

__0 zero to W__ vs. [Base p,
Characteristics = Line in slope for n_{b}; Collector n,
Characteristics = Curve for P_{c}; Emitter n+,
Characteristics = Curve for P_{e}, ... ]; Also known
as BJT dynamic behavior;

__Cell threshold voltage in V__ vs. [population:
qubit];
Characteristics = Multi-level cells' states in signal pattern; Note: Find your own vector;

__Design rules in µm__ vs. [Capacitance C_{ground},
Capacitance C_{total}, Capacitance C_{x}, Capacitance_{p-p}]; Characteristics =
[Line in slope; Curve; Straight line];

I__nput voltage V _{in} in V__ vs. [Output voltage V

I__nput voltage V _{in} in V__ vs. Output voltage V

__Power dissipation in mW by gate__ vs. Delay in ns by
each gate of [BiCMOS, CMOS, ECL, TTL, ... ];
Characteristics = Parallel lines in slope;

__Power supply voltage V _{DD} in V__ vs.
[Normalized delay in integer quantity, Normalized power dissipation in integer
quantity, ... ];
Characteristics = Consecutive lines in slope and curve;

__Time in ns__ vs. [A, B, Carry IN, Carry OUT, SUM]; Characteristics = Signal's pattern; Full adder
simulation;

__Time in ns__ vs. CLK, **cl**oc**k** [Data
Out, DDR, ... ]; Characteristics = Synchronous pattern;

__Time in ns__ vs. quantitative DFF, **D** type
**f**lip-**f**lop [CK, CK bar, D, Qm, Qs]; Characteristics = DFF transient I/O signal pattern;

__Time in ns__ vs. [Last adder stage Carry
IN, SUM (1), SUM (2), SUM (3), SUM (4), SUM (5), SUM (6), SUM (7), SUM (LSB),
SUM (MSB)]; Characteristics = Signal's pattern in propagation; 8 bit carry ripple adder;

__Time in s__ [any given time] vs. Clock
of [CLK, CLK, ... ];
Characteristics = Clock skew pattern as variation;