Materials AND circuits     Last updated on 2014/2558 10 8, a full moon day;

Before testing and engineering materials, dual band transmitter should be understood basically.

Solid-state physics makes circuits analysis and design, computer science makes how to exploit thoroughly and how to deploy scientifically, YIN YANG of chemical properties and physical properties make new nano products ...;

Al-Cu vs. Cu: Al-Cu and Cu in laminated metal film [2~3 layers] is design in comb electrode structure which can perform antenna duplexer [Also see: Fujitsu's SAW filter, SAW resonator];   Amperium wire, superconducting ... , with zero resistance (conduct > 100 times) 285 A 66 copper wire;   (antimony, stibnite, sulfur, ... ) also see: under sea, WHERE nearby underwater volcano (water) IFF excluding water, hyper dimensional lights ... ;    (Array (CMOS gate-array) (BGA) (FPGA) (PGA) (...) [some arrays are in packaging techniques]);   ASIC;

BiCMOS, Bipolar CMOS;  

CCP, Chip Carrier Packages;   Characteristics in 1D, 2D, 3D, 4D, ... where information flows how;   CMOS;   CMP, Chemical Mechanical Polishing;   CNT, Carbon Nanotube [C60; NEC laboratories' Dr. Sumio Iijima; 1991];   

(Design Rules (Active area rule) (Contact rule) (Distance constraint rule [dB heterodyned overlapped EM energy engineering]) (Electric arc rule) (Layout-design rule (Lambda rule) (Micron rule)) (Mass energy / A, B, C, D, ... , tree rule) (Metal rule) (Non-arc circumference rule [Wireless/Satellite engineering]) (Poly-Si rule) (Tangent line to non-arc circumference rule [Advanced optical engineering]) (...));   (Digital Circuits (Dynamic circuits (Domino logic circuits) (NORA logic circuits) (TSPC logic circuits) (...)) (Static circuits (Classical CMOS) (CVSL circuits) (Transmission-gate circuits) (...)) (...));   DIP [In common, max. pin count <=64];   DRC, Design Rule Check;   DSP;  

EOS, Electrical overstress;   ESD, Electrostatic discharge;  

FET [Also see: FET in Transistor.htm];   FOX, Field Oxide;   (FPGA (CLB) (I/O buffer) (Interconnection/structural programmable) (...));   FSM, Finite State Machines [Automata theory];   (Full adder (3 input (a) (b) (c)) (2 output (sum out) (carry out)) (...));  

GA, Gate Array;   GaAs, Gallium Arsenide;   GaAs MESFET;   Gallium nitride substrates [Also see: FPC];   Geometrical seems like physical but geometrical is not physical;

Holey fiber [Also see: Sumitomo];

I/O, Input/Output;   InGaAs, laser photo diodes; (Integration (ULSI) (VLSI) (...));  

(Lithography (E beam) (...));   LOCOS;  

Mask;   MCM, Multi Chip Modules;   Mercury Thallium Barium Calcium Copper Oxide, a substance for high temperature superconducting [Pg. 13, Force Fields, PHYSICS OF THE IMPOSSIBLE, Michio Kaku, 2008]; Mesoporous materials, structured/uniformed porous materials between 2 ~ 50 nm Canon's usage;   (Metal (Al) (GND) (Metal-1) (Metal-2) (VDD) (...));   Metal nano powder;   MMIC;   MOS, Metal Oxide Semiconductor;   (MOS structure (Metal gate electrode) (Insulating oxide layer [i.e. SiO2]) (Substrate) (...));   MOS transistor;   MOSFET;   MOSIS, MOS Implementation System;   MUX;  

n+;   nMOS, n channel MOS;  

Optical computing: MCP to Pixel to APD;  

p+;   (Packaging (CCP, Chip Carrier Packages) (DIP) (MCM, Multi-Chip Modules) (PGA) (QFP, Quad Flat Packs) (...));   PCB;   PDA;   Periodic Table;   Photonic crystals;   (Photoresist (negative photo-resist) (positive photo-resist) (...));   Physical and materials constant;   PIE, Proton Induced Exfoliation, 11 slight 11 micro n s, i.e. flexible and thin wafer s;   Pin pointing technique;   PLA;   pMOS, p channel MOS;   poly-si [Also see: Poly-Si in Transistor.htm];   PTH;  

QFP, Quad Flat Packs;  

RAM;   RPT, Repeated Transistors [Also see: non-repeatable transistors];  

(Schematic (Draft level) (Gate level) (Transistor level) (...));   SEM, Scanning Electron Microscope;   Si substrate;   Si3N4;   SiO2;   SMT;   (Substrate (Si) (...) ); superconductor magnets to levitate nonmagnetic materials i.e. diamagnets and paramagnets;  Swapping with 2 integer variables;  

Timing diagram [i.e. Based on clock CLK, VDD can be classified into BL & BL, CSL, DIO & DIO, DL & DL, PSAE, WL, ... , thus SRAM can be monitored] where top notch pin level computer systems security becomes available;     TiO2, Titanium dioxide's resistance changes WHEN and WHERE O2 exists, also see: O2 sensor;     TSPC;  

UV, one of the particles of light;

VDSM;   VLSI design flow (Y-Chart = Algorithm [Behavioral] to Processor [Structural] to Chip floor plan [Geometrical] to Finite state machine [Behavioral] to Register ALU [Structural] to Module placement [Geometrical] to Module description [Behavioral] to Leaf cell [Structural] to Cell placement [Geometrical] to Boolean logical equation [Behavioral] to Transistor [Structural] to Mask [Geometrical]);

W/L ratio;

(Yield (Chip-yield) (Functional-yield) (Parametric-yield) (...));