Transistor     Last updated on 2015/2558 2 3, a full moon day;

In common, since 1950s, making software logic gates deployable, hardware chips are made of transistors [transistor is semiconductor], and also known as TRANsfer ReSISTER; Vacuum tubes were used to do calculation of logic but slower and higher energy consumption; For faster processing speed and lower energy consumption, transistors have been used;   Transistors have been replaced vacuum tubes for a half century; Theoretically, basic logical calculations are based on Boolean Logic; Gate is made of transistors; Gates' input/output values in Truth Table have been used to calculate both advance logic and basic Boolean logic;

For novice system programmers: Apply Syntax vs. Semantic concept between Gate and Transistor, and notice that gates are more likely to be in software usage, and transistors are more likely to be in hardware usage, and study of gate vs. transistor should be in materials engineering and chemical/physical research development because material makes transistor, transistor makes logic gate;

Also see: NEC and NEC Electronics; Semiconductor;

Transistors Usages: Transistor (*RAM transistors) (Repeated transistors) (ROM transistors) (Unique transistors non-repeated) (...);

3D Transistor a.k.a. S-RACT;

a-Si, Amorphous Silicon TFT fabrication;   Ashing;

Band gap ;   Base Old usage; Behavior( (Alpha cutoff) (Gain bandwidth product) (...));   BJT, Bipolar Junction Transistor;   Bonding;   BOX layer SOI;  

Carbon Nanotube transistor NEC: development stage In 2005;   Carrier mobility [better portability];   Caulking;   (Cell layout (DIFF) (MET-1) (MET-2) (NWELL wells = tubs where n-type substrate creates p-well, p-type substrate creates n-well) (P+) (POLY) (...));   (Characteristic (DC) (Function) (...) );   Characteristics in 2D, 3D, 4D, ... where information flows how;   CMOS;   (CMOSFET phase controlled ((NFET gate electrode) (PFET gate electrode)) (...));   (Coating (Photo-resist) () );   Collector Old usage

D, Drain FET electrode;   Decoupling;   Depletion;   (Deposition (CVD, Chemical Vapor Deposition) (Sputtering method) (...) );   Dicing; Direct tunneling current;   (Distortion compensation (DPD, Digital Pre-Distortion));   Drain current [MOS transistor's drain current];   Drain voltage;

Emitter Old usage;   Encapsulation;   Epitaxial layer;   (Etching (Dry etched by gas Plasma etch) (Wet etched by liquid chemical Chemical etch; HF Acid etch; ) (...) );

FD SOI, Fully Depleted Silicon On Insulator transistor double gate in 2004 for SoC;   (FET (HEMT) (JFET, Junction Field Effect Transistor) (MOSFET, Metal Oxide Semiconductor FET));   (Film (Field-oxide film, insulation layer) (Metallic film) (Ni film) (Nitride film) (Oxide film) (Polysilicon film) (...) );

G, Gate FET electrode; Gain;   (Gate (MOS-transistor) (Poly-Si/high-k) (Poly-Si/SiO2) (...) );   (Gate depletion (Poly-Si) (...) );   (Gate dielectric (high-k) (HfSiON) (low-k low dielectric constant material [65nm in 2004] ) (...) );   (Gate electrode (Metal) (...) );   Gate leakage [the lower the gate leakage, the better the transistor is];   Gold fine wire;  

(HEMT (AlN) (GaN) (SiC) (...));

IFF using (electricity OR light beam) metamaterial ... ; Ingot;   (Inspection (Final inspection) (Sampling inspection) (Wafer inspection) (...) );   Ion implantation;   Island;

(Layer (Cover layer, after metallization) (Diffusion (p-type diffusion = n-type transistor) (...) )  (GaAs layer) (insulation layer, also known as gate oxide) (SiO2 layer) (...) );   (Layout (Cell layout) (Mask layout) (...));   Lead frame;   Leak current Back-gate bias must apply; Also see: Gate leakage;   Library One library may contains hundreds of cells such as flip-flops, gates, inverters, latches, ... ;   (Logic circuit design (CAD) (IC function) (Layout design) (Mask pattern) (...) );   LOP transitor, Low Operation Power [In 2004, micro-amp, OR nano-amp are recommended];   LSI If signal delays because of line to line F, low-k is recommended to reduce capacitance;   Also see:   Hitachi;   LSTP, Low Standby Power;

MESFET, Metal Semiconductor Field Effect Transistor;   Metal gate a part of SOI transistor;   Metallization; Modular structure;   Mounting;

Ni, Nickel;   NMOS;

Operating speed;

p-Si, Poly Silicon TFT fabrication;   Patterning;   Photo-mask;   Pinchoff;   PMOS;   Poly-Si, Polycrystalline Silicon;   Polycell = Standard cell;    Prober;   (Process procedure (Full silicidation annealing) (Micro-fabrication (Transistors) (Diodes)) (Wafer fabrication) (...) );   (Processing (BE) (FE) );

(Ratio of composition (Ni/Si) (...) ); RCAT, Recess Channel Array Transistor, 50nm, Samsung, 2006;

S, Source FET electrode;   Saturation state;   Silicidation;   Silver paste resin;   SoC, System-on-Chip;   SOG, Sea of Gates;   SOI, Silicon On Insulator;   SOI transistor Tunable threshold V tech = Metal gate + variable threshold voltage by ion implantation, Sputtering method;   (Stepper (UV photo-mask) (...));   (Stripping (Photo-resist) (...) );   Sub-threshold current;  

Tester;   TFT, Thin-film transistor;   Trans-conductance JFET Analog dynamic mutual conductance;

Ultraviolet beam radiation etches microscopic transistors onto wafer, WHERE wafer is made of silicon, therefore, silicon transistors ... , therefore to categorize various types and levels;

Vth, Threshold voltage one of the most important parameters of CMOS;

(Wafer (Wafer fabrication (Lithography method) (...) )  (Wafer inspection, where human logic becomes the most important also see Tester and Prober) (...) );


Basic understanding of transistors' functions are shown below:

NPN, PNP Current Flow: from Emitter to Collector (without modulating)  
  N P N    
Emitter   _ + _   Collector
  P N P    
Emitter   + _ +   Collector
  _         _  
Source     Drain
FET Current Flow: from Source to Drain (with modulating / electric field at Gate)

Also see: Basic gates [ *gate: ]; Symbolic schematic gates;

Basic understanding of Truth Table is shown below:

NAND gate NAND element; NAND operation non-conjunction, NOT-BOTH operation; NAND (gate, circuit) not - and;

For Monbusho level developers only: with brunching factor 2 [larger the factor number, harder the logic], reversely engineer from leaf depths [deeper the tree depth, longer the path]  to root, use of A, B, C, D, E, ... , and fully distributed connection ((N (N-1)) / 2 ), and make advance nama logic for Asimo Ukon and later ... ;